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Rev. 5.00, 09/03, page 726 of 760
32-Bit Bus Width
Pin
Byte
Access
(Address
4n)
Byte
Access
(Address
4n + 1)
Byte
Access
(Address
4n + 2)
Byte
Access
(Address
4n + 3)
Word
Access
(Address
4n)
Word
Access
(Address
4n + 2)
Longword
Access
CS6 to CS2, CS0 Enabled Enabled Enabled Enabled Enabled Enabled Enabled
R Low Low Low Low Low Low LowRD
W High High High High High High High
R High High High High High High HighRD/WR
W Low Low Low Low Low Low Low
BS Enabled Enabled Enabled Enabled Enabled Enabled Enabled
RAS3U/PTE[2] High High High High High High High
RAS3L/PTJ[0] High High High High High High High
CASL/PTJ[2] High High High High High High High
CASU/PTJ[3] High High High High High High High
R High High High High High High HighWE0/DQMLL
W Low High High High Low High Low
R High High High High High High HighWE1/DQMLU/WE
W High Low High High Low High Low
R High High High High High High HighWE2/DQMUL/
ICIORD/PTK[6]
W High High Low High High Low Low
R High High High High High High HighWE3/DQMUU/
ICIOWR/PTK[7]
W High High High Low High Low Low
CE2A/PTE[4] High High High High High High High
CE2B/PTE[5] High High High High High High High
CKE/PTK[5] Disabled Disabled Disabled Disabled Disabled Disabled Disabled
WAIT Enabled
*
1
Enabled
*
1
Enabled
*
1
Enabled
*
1
Enabled
*
1
Enabled
*
1
Enabled
*
1
IOIS16/PTG[7] Disabled Disabled Disabled Disabled Disabled Disabled Disabled
A25 to A0 Address Address Address Address Address Address Address
D7 to D0
Valid
data
Invalid
data
Invalid
data
Invalid
data
Valid
data
Invalid
data
Valid
data
D15 to D8 Invalid
data
Valid
data
Invalid
data
Invalid
data
Valid
data
Invalid
data
Valid
data
D23 to D16 Invalid
data
Invalid
data
Valid
data
Invalid
data
Invalid
data
Valid
data
Valid
data
D31 to D24
Invalid
data
Invalid
data
Invalid
data
Valid
data
Invalid
data
Valid
data
Valid
data
Notes: 1. Disabled when WCR2 register wait setting is 0.
2. Unused data pins should be switched to the port function, or pulled up.