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Rev. 5.00, 09/03, page 131 of 760
6.3 INTC Registers
6.3.1 Interrupt Priority Registers A to E (IPRA–IPRE)
Interrupt priority registers A to E (IPRA to IPRE) are 16-bit readable/writable registers in which
priority levels from 0 to 15 are set for on-chip peripheral module, IRQ, and PINT interrupts. These
registers are initialized to H'0000 by a power-on reset or manual reset, but are not initialized in
standby mode.
Bit: 15 14 13 12 11 10 9 8
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit:76543210
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 6.7 lists the relationship between the interrupt sources and the IPRA—IPRE bits.
Table 6.7 Interrupt Request Sources and IPRA–IPRE
Register Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0
IPRA TMU0 TMU1 TMU2 RTC
IPRB WDT REF SCI0 Reserved
*
IPRC IRQ3 IRQ2 IRQ1 IRQ0
IPRD PINT0 to PINT7 PINT8 to PINT15 IRQ5 IRQ4
IPRE DMAC IrDA SCIF ADC
Note: * Always read as 0. Only 0 should be written.
As shown in table 6.7, on-chip peripheral module, IRQ, or PINT interrupts are assigned to four 4-
bit groups in each register. These 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to
0) are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking
is requested); H'F is priority level 15 (the highest level). A reset initializes IPRA–IPRE to H'0000.