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Rev. 5.00, 09/03, page 588 of 760
19.2.2 Port A Data Register (PADR)
Bit:76543210
PA7DT PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The port A data register (PADR) is an 8-bit readable/writable register that stores data for pins
PTA7 to PTA0. Bits PA7DT to PA0DT correspond to pins PTA7 to PTA0. When the pin function
is general output port, if the port is read the value of the corresponding PADR bit is returned
directly. When the function is general input port, if the port is read the corresponding pin level is
read. Table 19.2 shows the function of PADR.
PADR is initialized to H'00 by a power-on reset. It retains its previous value in standby mode and
sleep mode, and in a manual reset.
Table 19.2 Port A Data Register (PADR) Read/Write Operations
PAnMD1 PAnMD0 Pin State Read Write
0 0 Other function
(See table 18.1)
PADR value Value is written to PADR, but does not
affect pin state
1 Output PADR value Write value is output from pin
1 0 Input (Pull-up
MOS on)
Pin state Value is written to PADR, but does not
affect pin state
1 Input (Pull-up
MOS off)
Pin state Value is written to PADR, but does not
affect pin state
(n = 7 to 0)