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Rev. 5.00, 09/03, page 701 of 760
CKIO
T
pcm1
T
pcm2
T
pcm1
T
pcm2
T
pcm1
T
pcm2
T
pcm1
T
pcm2
A25 to A4
A3 to A0
CExx
RD/WR
RD
D15 to D0
BS
DACKn
t
AD
t
AD
t
CSD1
t
RWD
t
CSD1
t
RWD
t
AD
t
AD
t
AD
t
AD
t
DAKD1
t
RSD
t
RSD
t
RDH1
t
RDH1
t
RSD
t
RSD
t
BSD
t
BSD
t
BSD
t
BSD
t
RDS1
t
RDS1
Note: Even though burst mode is set, write cycle operation is the same as in normal mode.
(read)
(read)
t
DAKD1
Figure 23.42 PCMCIA Memory Bus Cycle
(Burst Read, TED = 0, TEH = 0, No Wait)