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Rev. 5.00, 09/03, page 108 of 760
Table 5.5 Way Replacement when Instructions Except for PREF Instruction Ended Up in
a Cache Miss
DSP bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be replaced
0 ****Depends on LRU (table 5.2)
1 * 0 * 0 Depends on LRU (table 5.2)
1 * 0 * 1 Depends on LRU (table 5.6)
1 * 1 * 0 Depends on LRU (table 5.7)
1 * 1 * 1 Depends on LRU (table 5.8)
*: Don't care
Do not set as W3LOAD=1 and also W2LOAD=1
Table 5.6 LRU and Way Replacement (when W2LOCK=1)
LRU (5–0) Way to be Replaced
000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 3
000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 1
101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111 0
Table 5.7 LRU and Way Replacement (when W3LOCK=1)
LRU (5–0) Way to be Replaced
000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 2
000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 1
110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0
Table 5.8 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1)
LRU (5–0) Way to be Replaced
000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111,
010100, 010110, 011110, 011111
1
100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001,
111011, 111100, 111110, 111111
0