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Rev. 5.00, 09/03, page 607 of 760
19.12 Port L
Port L is an 8-bit input port with the pin configuration shown in figure 19.11.
PTL7 (input) / AN7 (input) / DA0 (input)
PTL6 (input) / AN6 (input) / DA1 (input)
PTL5 (input) / AN5 (input)
PTL4 (input) / AN4 (input)
PTL3 (input) / AN3 (input)
PTL2 (input) / AN2 (input)
PTL1 (input) / AN1 (input)
PTL0 (input) / AN0 (input)
Port L
Figure 19.11 Port L
19.12.1 Register Description
Table 19.21 summarizes the port L register.
Table 19.21 Port L Register
Name Abbreviation R/W Initial Value Address Access Size
Port L data register PLDR R H'00 H'04000134
(H'A4000134)
*
8
Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either
access this register from the P2 area of logical space or else make an appropriate setting
using the MMU so that this register is not cached.
* When address translation by the MMU does not apply, the address in parentheses
should be used.