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Rev. 5.00, 09/03, page 439 of 760
Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if SCTDR does not contain new transmit data when the MSB is transmitted.
Bit 2: TEIE Description
0 Transmit-end interrupt (TEI) requests are disabled
*
(Initial value)
1 Transmit-end interrupt (TEI) requests are enabled
*
Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register
(SCSSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end
(TEND) bit to 0, or by clearing the TEIE bit to 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): Select the SCI clock source and enable or
disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the
SCK pin can be used for serial clock output or serial clock input.
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external
clock source is selected (CKE1 = 1). Before selecting the SCI operating mode in the serial mode
register (SCSMR), set CKE1 and CKE0. For further details on selection of the SCI clock source,
see table 14.10 in section 14.3, Operation.
Bit 1:
CKE1
Bit 0:
CKE0 Description
0 0 Asynchronous mode Internal clock, SCK pin used for input pin (input signal
is ignored) (Initial value)
Synchronous mode Internal clock, SCK pin used for synchronous clock
output (Initial value)
1 Asynchronous mode Internal clock, SCK pin used for clock output
*
1
Synchronous mode Internal clock, SCK pin used for synchronous clock
output
1 0 Asynchronous mode External clock, SCK pin used for clock input
*
2
Synchronous mode External clock, SCK pin used for synchronous clock
input
1 Asynchronous mode External clock, SCK pin used for clock input
*
2
Synchronous mode External clock, SCK pin used for synchronous clock
input
Notes: 1. The output clock frequency is the same as the bit rate.
2. The input clock frequency is 16 times the bit rate.