Rev. 5.00, 09/03, page 6 of 760
1.2 Block Diagram
MMU
TLB
SH-3
CPU
UBC
SCI
TMU
RTC
IrDA
SCIF
ADC
DAC
AUD
BRIDGE
DMAC
CMT
I/O port
External bus
interface
BSC
CCN
CACHE
UDI
INTC
CPG/WDT
Peripheral bus 1
Peripheral bus 2
L bus
I bus 1I bus 2
Legend:
ADC:
AUD:
BSC:
CACHE:
CCN:
CMT:
CPG/WDT:
CPU:
DAC:
DMAC:
UDI:
A/D converter
Advanced user debugger
Bus state controller
Cache memory
Cache memory controller
Compare match timer
Clock pulse generator/watchdog timer
Central processing unit
D/A converter
Direct memory access controller
User debugging interface
INTC:
IrDA:
MMU:
RTC:
SCI:
SCIF:
TLB:
TMU:
UBC:
Interrupt controller
Serial communicatiion interface (with IrDA)
Memory management unit
Realtime clock
Serial communication interface (with smart card interface)
Serial communication interface (with FIFO)
Address translation buffer
Timer unit
User break controller
Figure 1.1 Block Diagram