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Rev. 5.00, 09/03, page 695 of 760
CKIO
A12 or A10
RD/WR
CSn
RAS
CAS
BS
DQMxx
CKE
A25 to A16
A15 to A0
Tp
Tpw Tr Trw Tc1 Tc2 Tc3
D31 to
D0
t
AD
t
AD
t
CSD3
t
CSD3
t
RWD
t
RWD
t
RWD
t
RWD
t
RASD2
t
RASD2
t
RASD2
t
RASD2
t
DQMD
t
DQMD
t
DQMD
t
WDD2
t
WDD2
t
BSD
t
BSD
(High)
t
AD
t
AD
t
AD
t
AD
t
AD
t
AD
Td4
Write command
Column address
t
CASD2
t
CASD2
Row
address
Row
address
t
AD
t
AD
Row address
t
DAKD1
t
DAKD1
DACKn
Figure 23.36 Synchronous DRAM Burst Write Bus Cycle
(RAS Down, Different Row Address, TPC = 1, RCD = 1)