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Rev. 5.00, 09/03, page 527 of 760
Upper 8 bits: 15 14 13 12 11 10 9 8
PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0
Initial value:00000000
R/W:RRRRRRRR
Bits 15 to 12—Number of Parity Errors 3 to 0 (PER3 to PER0): Indicate the quantity of data
including a parity error in the receive data stored in the receive FIFO data register (SCFRDR).
The value indicated by bits 15 to 12 represents the number of parity errors in SCFRDR.
Bits 11 to 8—Number of Framing Errors 3 to 0 (FER3 to FER0): Indicate the quantity of data
including a framing error in the receive data stored in SCFRDR. The value indicated by bits 11 to
8 represents the number of framing errors in SCFRDR.
16.2.8 Bit Rate Register (SCBRR)
The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a reset and in
module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.
Bit:76543210
Initial value:11111111
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The SCBRR setting is calculated as follows:
Asynchronous mode:
N =
Pφ
64 × 2
2n – 1
× B
× 10
6
– 1
B: Bit rate (bits/s)
N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n, see table 16.3.)