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Rev. 5.00, 09/03, page 147 of 760
Number of States
Item NMI IRQ PINT
Peripheral
Modules Notes
Response
time
Total (5.5 + X)
× Icyc
+ 1.5
× Pcyc
*
5
(5.5 + X)
× Icyc
+ 0.5 × Bcyc
+ 0.5 × Pcyc
(5.5 + X)
× Icyc
+ 1 × Bcyc
+ 4.5 ×
Pcyc
*
4
(5.5 + X)
× Icyc
+ 3.5 ×
Pcyc
*
5
(5.5 + X)
× Icyc
+ 3 × Pcyc
*
6
Minimum
case
*
2
7.5 16.5 12.5 8.5
*
5
/11.5
*
6
At 60-MHz (CKIO
= 30) operation:
0.13–0.28 µs
Maximum
case
*
3
8.5 + S 26.5 + S 18.5 + S 10.5 + S
*
5
16.5 + S
*
6
At 60-MHz (CKIO
= 15) operation:
0.26–0.56 µs (in
case of operand
cache-hit)
At 60-MHz (CKIO
= 15) operation:
0.29–0.59 µs
(when external
memory access is
performed with
wait = 0)
Icyc: Duration of one cycle of internal clock supplied to CPU.
Bcyc: Duration of one CKIO cycle.
Pcyc: Duration of one cycle of peripheral clock supplied to peripheral modules.
Notes: 1. S also includes the memory access wait time.
The processing requiring the maximum execution time is LDC.L @Rm+, SR. When the
memory access is a cache-hit, this requires seven instruction execution cycles. When
the external access is performed, the corresponding number of cycles must be added.
There are also instructions that perform two external memory accesses; if the external
memory access is slow, the number of instruction execution cycles will increase
accordingly.
2. The internal clock:CKIO:peripheral clock ratio is 2:1:1.
3. The internal clock:CKIO:peripheral clock ratio is 4:1:1.
4. IRQ mode
5. Modules: TMU, RTC, SCI, WDT, REFC
6. Modules: DMAC, ADC, IrDA, SCIF