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Rev. 5.00, 09/03, page 363 of 760
11.3.5 Number of Bus Cycle States and D
DD
DR
RR
RE
EE
EQ
QQ
Q Pin Sampling Timing
Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states
is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master.
For details, see section 10, Bus State Controller (BSC).
D
DD
DR
RR
RE
EE
EQ
QQ
Q Pin Sampling Timing: In external request mode, the DREQ pin is sampled by clock pulse
(CKIO) falling edge or low level detection. When DREQ input is detected, a DMAC bus cycle is
generated and DMA transfer performed, at the earliest, three states later.
The second and subsequent DREQ sampling operations are started two cycles after the first
sample.
Operation
• Cycle-Steal Mode
In cycle-steal mode, the DREQ sampling timing is the same regardless of whether level or
edge detection is used.
For example, in figure 11.15 (cycle-steal mode, level input), DMAC transfer begins, at the
earliest, three cycles after the first sampling is performed. The second sampling is started two
cycles after the first. If DREQ is not detected at this time, sampling is performed in each
subsequent cycle.
Thus, DREQ sampling is performed one step in advance. The third sampling operation is not
performed until the idle cycle following the end of the first DMA transfer.
The above conditions are the same whatever the number of CPU transfer cycles, as shown in
figure 11.16. The above conditions are also the same whatever the number of DMA transfer
cycles, as shown in figure 11.17.
DACK is output in a read in the example in figure 11.15, and in a write in the example in
figure 11.16. In both cases, DACK is output for the same duration as CSn.
Figure 11.18 shows an example in which sampling is executed in all subsequent cycles when
DREQ cannot be detected.