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Rev. 5.00, 09/03, page 369 of 760
CKIO
DRAK
Bus cycle
DREQ
DACK
(RD output)
CPU CPU
DMAC(W)
DMAC(R)
DMAC(W)
DMAC(R)
CPU
High HighHigh High
3rd sampling is performed,
but since there is no DREQ falling edge,
per-cycle sampling starts
2nd sampling is performed,
but since there is no DREQ falling edge,
per-cycle sampling starts
1st sampling 2nd sampling 3rd sampling
Note: When a DREQ falling edge is detected, DREQ must be high for at least one cycle before the sampling point.
Figure 11.19 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles)