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Rev. 5.00, 09/03, page 168 of 760
Bits 30 to 28—Instruction Decode Pointer (PID2 to PID0): PID is a 3-bit binary pointer (0–7).
These bits indicate the instruction buffer number which stores the last executed instruction before
branch.
Bits 30 to 28:
PID Description
Even PID indicates the instruction buffer number.
Odd PiD+2 indicates the instruction buffer number
Bits 27 to 0—Branch Source Address (BSA27 to BSA0): These bits store the last fetched
address before branch.
7.2.12 Branch Destination Register (BRDR)
BRDR is a 32-bit read register. BRDR stores the branch destination fetch address. BRDR has the
flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRDR is read and
also initialized by power-on resets or manual resets. Other bits are not initialized by resets. Eight
BRDR registers have queue structure and a stored register is shifted every branch.
Bit: 31 30 29 28 27 26 25 24
DVF — — — BDA27 BDA26 BDA25 BDA24
Initial value: 0 *******
R/W:RRRRRRRR
Bit: 23 22 21 20 19 18 17 16
BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16
Initial value: ********
R/W:RRRRRRRR
Bit: 15 14 13 12 11 10 9 8
BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8
Initial value: ********
R/W:RRRRRRRR
Bit:76543210
BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0
Initial value: ********
R/W:RRRRRRRR
Note: * Undefined value