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Rev. 5.00, 09/03, page 685 of 760
CKIO
A12 or A10
RD/WR
CSn
RAS
CAS
BS
DQMxx
CKE
A25 to A16
A15 to A0
Tr
Tc1 (Trwl) (Tpc)
(High)
D31 to D0
tAD
Row address
Row address
Write A
command
Row address Column address
tAD
tAD
tCSD3
tRWD
tRASD2
tAD
tADtAD
tAD
tAD
tCSD3
tRWDtRWD
tRASD2
tCASD2
tDQMD
tWDD2
tBSD
tDQMD
tWDH2
tBSD
tCASD2
t
DAKD1
t
DAKD1
DACKn
Figure 23.26 Synchronous DRAM Write Bus Cycle (RCD =
==
= 0, TPC =
==
= 0, TRWL = 0)