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Rev. 5.00, 09/03, page 684 of 760
CKIO
A12 or A10
RD/WR
CSn
RAS
CAS
BS
DQMxx
CKE
A25 to A16
A15 to A0
Tr Trw Tc1 Tc2 Tc3 Tc4/Td1
Td2 Td3 Td4 (Tpc)
D31 to D0
(read)
tAD tAD
tAD
tAD tAD
tAD tAD tAD tAD
tAD
tCSD3
tRWD
tDQMD
tRDS2
tBSD tBSD
tRDH2 tRDS2 tRDH2
tCSD3
tRWD
tRASD2
tRASD2
tCASD2
tDQMD
tCASD2
Row address
Row
address
Row
address
Read command
(High)
Column address (1-4)
t
DAKD1
t
DAKD1
DACKn
Figure 23.25 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read ×
××
× 4), RCD =
==
= 1,
CAS Latency =
==
= 3, TPC =
==
= 0)