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Rev. 5.00, 09/03, page 341 of 760
Bit 6—D
DD
DR
RR
RE
EE
EQ
QQ
Q Select Bit (DS): Selects low-level or falling-edge detection as the sampling method
for the DREQ pin used in external request mode.
This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and
CHCR3; 0 is read if this bit is read. The write value should always be 0.
In channels 0 and 1, if an on-chip peripheral module is specified as a transfer request source or an
auto-request is specified, the specification of this bit is ignored and falling-edge detection is fixed
except in an auto-request.
Bit 6: DS Description
0 DREQ detected by low level (Initial value)
1 DREQ detected at falling edge
Bit 5—Transmit Mode (TM): Specifies the bus mode when transferring data.
Bit 5: TM Description
0 Cycle-steal mode (Initial value)
1 Burst mode
Bits 4 and 3—Transmit Size Bits 1 and 0 (TS1, TS0): Specify the size of data to be transferred.
Bit 4: TS1 Bit 3: TS0 Description
0 0 Byte size (8 bits) (Initial value)
0 1 Word size (16 bits)
1 0 Longword size (32 bits)
1 1 16-byte unit (4 longword transfers)
Bit 2—Interrupt Enable Bit (IE): If this bit is set to 1, an interrupt is requested on completion of
the number of data transfers specified in DMATCR (i.e. when TE = 1).
Bit 2: IE Description
0 Interrupt request is not generated on completion of data transfers
specified in DMATCR (Initial value)
1 Interrupt request is generated on completion of data transfers specified
in DMATCR