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Rev. 5.00, 09/03, page 690 of 760
A25 to A16
(High)
t
AD
t
AD
t
AD
t
CASD2
t
CSD3
t
RWD
t
DQMD
t
BSD
t
RDH2
t
RDS2
t
RDH2
t
RDS2
t
BSD
t
RASD2
t
CASD2
t
DQMD
t
RWD
t
CSD3
t
AD
t
AD
t
AD
Tc1 Tc2 Tc3/Td1 Tc4/Td2 Td3 Td4
CKIO
A12 or A10
A15 to A0
CSn
RD/WR
RAS
CAS
DQMxx
D31 to D0
BS
CKE
Row address
DACKn
t
DAKD1
t
DAKD1
Column address
Read command
Figure 23.31 Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Same Row Address, CAS Latency = 2)