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Rev. 5.00, 09/03, page 335 of 760
11.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)
DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 24-bit readable/writable registers
that specify the DMA transfer count (bytes, words, or longwords). The number of transfers is 1
when the setting is H'000001, and 16,777,216 (the maximum) when H'000000 is set. During a
DMA transfer, these registers indicate the remaining number of transfers.
In 16-byte transfer, one 16-byte transfer (128 bits) is counted as one.
Writing to upper eight bits in DMATCR is invalid; 0s are read if these bits are read. The write
value should always be 0.
An undefined value will be returned in a reset. The previous value is retained in standby mode.
Bit: 31 30 29 28 27 26 25 24
Initial value:————————
R/W:RRRRRRRR
Bit: 23 22 21 20 ... 0
...
Initial value:———— ... —
R/W: R/W R/W R/W R/W ... R/W