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Rev. 5.00, 09/03, page 348 of 760
request signal. The source of the transfer request does not have to be the data transfer source or
destination. When RXI is set as the transfer request, however, the transfer source must be the SCI's
receive data register (RDR). Likewise, when TXI is set as the transfer request, the transfer source
must be the SCI's transmit data register (TDR). If the transfer requester is the A/D converter, the
data transfer source must be the A/D data register (ADDR).
Table 11.4 Selecting On-Chip Peripheral Module Request Modes with RS3-0 Bits
RS3 RS2 RS1 RS0
DMA
Transfer
Request
Source DMA Transfer Request Signal Source
Desti-
nation Bus Mode
1010IrDA
transmitter
TXI1 (IrDA transmit-data-empty
interrupt transfer request)
Any
*
TDR1 Cycle-steal
1011IrDA
receiver
RXI1 (IrDA receive-data-full
interrupt transfer request)
RDR1 Any
*
Cycle-steal
1100SCIF
transmitter
TXI2 (SCIF transmit-data-empty
interrupt transfer request)
Any
*
TDR2 Cycle-steal
1101SCIF
receiver
RXI2 (SCIF receive-data-full
interrupt transfer request)
RDR1 Any
*
Cycle-steal
1110A/D
converter
ADI (A/D conversion end
interrupt)
ADDR Any
*
Cycle-steal
1 1 1 1 CMT CMI (Compare match timer
interrupt)
Any
*
Any
*
Burst/
cycle-steal
ADDR: A/D data register of A/D converter
Note: * External memory, memory-mapped external device, on-chip peripheral module (This
applies only to IrDA, SCIF, A/D converter, D/A converter, and I/O ports.)
When outputting transfer requests from on-chip peripheral modules, the appropriate interrupt
enable bits must be set to output the interrupt signals.
If the interrupt request signal of the on-chip peripheral module is used as a DMA transfer request
signal, an interrupt is not sent to the CPU.
The DMA transfer request signals in table 11.4 are automatically discontinued when the
corresponding DMA transfer is performed. If cycle-steal mode is being employed, they are
withdrawn at the first transfer; if burst mode is being used, they are discontinued at the last
transfer.