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Rev. 5.00, 09/03, page 376 of 760
11.4 Compare Match Timer (CMT)
11.4.1 Overview
The DMAC has an on-chip compare match timer (CMT) to generate DMA transfer requests. The
CMT has a 16-bit counter.
Features
The CMT has the following features:
• Four types of counter input clock can be selected
One of four internal clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) can be selected.
• Generates a DMA transfer request when compare match occurs.
Block Diagram
Figure 11.24 shows a block diagram of the CMT.
Internal bus
Bus
interface
Control circuit Clock selection
CMSTR
CMCSR0
CMCOR0
Comparator
CMCNT0
Module bus
CMT
Pφ/4 Pφ/8 Pφ/16 Pφ/64
CMSTR:
CMCSR0:
CMCOR0:
CMCNT0:
Compare match timer start register
Compare match timer control/status register 0
Compare match timer constant register 0
Compare match timer counter 0
Figure 11.24 Block Diagram of CMT