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Rev. 5.00, 09/03, page 608 of 760
19.12.2 Port L Data Register (PLDR)
Bit:76543210
PL7DT PL6DT PL5DT PL4DT PL3DT PL2DT PL1DT PL0DT
Initial value:00000000
R/W:RRRRRRRR
The port L data register (PLDR) is an 8-bit read-only register that stores data for pins PTL7 to
PTL0. Bits PL7DT to PL0DT correspond to pins PTL7 to PTL0. When the function is general
input port, if the port is read, the corresponding pin level is read. Table 19.22 shows the function
of PLDR.
PKDR is initialized to H'00 by power-on reset. It retains its previous value in software standby
mode and sleep mode, and in a manual reset.
The port L is also used as an analog pin, therefore does not have a pull-up MOS.
Table 19.22 Port L Data Register (PLDR) Read/Write Operation
PLnMD1 PLnMD0 Pin State Read Write
0 0 Other function
(see table 18.1)
H'00 Ignored (no effect on pin state)
1 Reserved H'00 Ignored (no effect on pin state)
1 0 Input Pin state Ignored (no effect on pin state)
1 Input Pin state Ignored (no effect on pin state)
(n = 0 to 7)