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Rev. 5.00, 09/03, page 255 of 760
Bit 0—Refresh Count Overflow Limit Select (LMTS): Indicates the count limit value to be
compared to the number of refreshes indicated in the refresh count register (RFCR). When the
value in RFCR overflows the value specified by LMTS, the OVF flag is set.
Bit 0: LMTS Description
0 Count limit value is 1024 (Initial value)
1 Count limit value is 512
10.2.9 Refresh Timer Counter (RTCNT)
RTCNT is a 16-bit register containing a readable/writable 8-bit counter that counts up on an input
clock. The clock select bits (CKS2–CKS0) in RTCSR select the input clock. When RTCNT
matches RTCOR, the CMF bit in RTCSR is set and RTCNT is cleared. RTCNT is initialized to
H'00 by a power-on reset, but continues incrementing after a manual reset. It is not initialized in
standby mode, but holds its contents.
Note: The method of writing to RTCNT differs from that for general registers to ensure that
RTCNT is not rewritten incorrectly. Use a word transfer instruction to set the upper byte
as B'10100101 and the lower byte as the write data. For details, see section 10.2.12,
Cautions on Accessing Refresh Control Related Registers.
Bit: 15 14 13 12 11 10 9 8
Initial value:00000000
R/W:————————
Bit:76543210
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W