Filter
Top Products
Rev. 5.00, 09/03, page 368 of 760
CKIO
DRAK
Bus cycle
DREQ
DACK
(RD output)
CPU CPU
DMAC(W)
DMAC(R)
DMAC(W)
DMAC(R)
CPU
3rd sampling is performed,
but since DREQ is high,
per-cycle sampling starts
2nd sampling is performed,
but since DREQ is high,
per-cycle sampling starts
1st sampling 2nd sampling 3rd sampling
Figure 11.18 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, D
DD
DR
RR
RE
EE
EQ
QQ
Q Input Delayed)