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Rev. 5.00, 09/03, page 596 of 760
19.6.2 Port E Data Register (PEDR)
Bit:76543210
PE7DT PE6DT PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The port E data register (PEDR) is an 8-bit readable/writable register that stores data for pins
PTE7 to PTE0. Bits PE7DT to PE0DT correspond to pins PTE7 to PTE0. When the pin function is
general output port, if the port is read the value of the corresponding PEDR bit is returned directly.
When the function is general input port, if the port is read the corresponding pin level is read.
Table 19.10 shows the function of PEDR.
PEDR is initialized to H'00 by a power-on reset, after which the general input port function (pull-
up MOS on) is set as the initial pin function, and the corresponding pin levels are read. It retains
its previous value in standby mode and sleep mode, and in a manual reset.
Table 19.10 Port E Data Register (PEDR) Read/Write Operations
PEnMD1 PEnMD0 Pin State Read Write
0 0 Other function
(see table 18.1)
PEDR value Value is written to PEDR, but does not
affect pin state
1 Output PEDR value Write value is output from pin
1 0 Input (Pull-up
MOS on)
Pin state Value is written to PEDR, but does not
affect pin state
1 Input (Pull-up
MOS off)
Pin state Value is written to PEDR, but does not
affect pin state
(n = 0 to 7)