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Rev. 5.00, 09/03, page 709 of 760
DRAK0/1
CKIO
t
DRAKD
t
DRAKD
Figure 23.54 DRAK Output Timing
23.3.9 UDI-Related Pin Timing
Table 23.9 UDI-Related Pin Timing
VccQ = 3.3 ± 0.3V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3V, Ta = –20 to 75°C
Item Symbol Min Max Unit Figure
TCK cycle time t
TCKCYC
50 — ns 23.55
TCK high pulse width t
TCKH
12 — ns
TCK low pulse width t
TCKL
12 — ns
TCK rise/fall time t
TCKf
— 4ns
TRST setup time t
TRSTS
12 — ns 23.56
TRST hold time t
TRSTH
50 — t
cyc
TDI setup time t
TDIS
10 — ns 23.57
TDI hold time t
TDIH
10 — ns
TMS setup time t
TMSS
10 — ns
TMS hold time t
TMSH
10 — ns
TDO delay time t
TDOD
— 16 ns
ASEMD0 setup time t
ASEMDH
12 — ns 23.58
ASEMD0 hold time t
ASEMDS
12 — ns
t
TCKL
t
TCKf
V
IL
V
IL
V
IH
V
IH
V
IH
1/2
VccQ
1/2
VccQ
Note: When clock is input from TCK pin
t
TCKf
t
TCKH
t
TCKCYC
Figure 23.55 TCK Input Timing