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Rev. 5.00, 09/03, page 164 of 760
Bit 13—DMAC Condition Match Flag A (SCMFDA): When the on-chip DMAC bus cycle
condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 into this bit.
Bit 13:
SCMFDA Description
0 The DMAC cycle condition for channel A does not match (Initial value)
1 The DMAC cycle condition for channel A matches
Bit 12—DMAC Condition Match Flag B (SCMFDB): When the on-chip DMAC bus cycle
condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 into this bit.
Bit 12:
SCMFDB Description
0 The DMAC cycle condition for channel B does not match (Initial value)
1 The DMAC cycle condition for channel B matches
Bit 11—PC Trace Enable (PCTE): Enables PC trace.
Bit 11: PCTE Description
0 Disables PC trace (Initial value)
1 Enables PC trace
Bit 10—PC Break Select A (PCBA): Selects the break timing of the instruction fetch cycle for
channel A as before or after instruction execution.
Bit 10: PCBA Description
0 PC break of channel A is set before instruction execution (Initial value)
1 PC break of channel A is set after instruction execution
Bits 9 and 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—Data Break Enable B (DBEB): Selects whether or not the data bus condition is included
in the break condition of channel B.
Bit 7: DBEB Description
0 No data bus condition is included in the condition of channel B (Initial value)
1 The data bus condition is included in the condition of channel B