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Rev. 5.00, 09/03, page 187 of 760
8.3 Sleep Mode
8.3.1 Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral
modules continue to run in sleep mode and the clock continues to be output to the CKIO and
CKIO2 pins. In sleep mode, the STATUS1 pin is set high and the STATUS0 pin low.
8.3.2 Canceling Sleep Mode
Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, on-chip peripheral module, PINT) or
reset. Interrupts are accepted in sleep mode even when the BL bit in the SR register is 1. If
necessary, save SPC and SSR to the stack before executing the SLEEP instruction.
Canceling with an Interrupt: When an NMI, IRQ, IRL or on-chip peripheral module interrupt
occurs, sleep mode is canceled and interrupt exception handling is executed. A code indicating the
interrupt source is set in the INTEVT and INTEVT2 registers.
Canceling with a Reset: Sleep mode is canceled by a power-on reset or a manual reset.
8.3.3 Precautions when Using the Sleep Mode
DMAC transfers should not be performed in the sleep mode under conditions other than when the
clock ratio of Iφ (on-chip clock) to Bφ (bus clock) is 1:1.