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Rev. 5.00, 09/03, page 508 of 760
0 185 371 0 185 371 0
Base clock
Receive
data (RxD)
Synchro-
nization
sampling
timing
Data
sampling
timing
186 clock cycles
372 clock cycles
Start
bit
D0 D1
Figure 15.8 Receive Data Sampling Timing in Smart Card Mode
The receive margin is found from the following equation:
For smart card mode:
M = (0.5 − )
1
2N
D − 0.5
N
− (L − 0.5)F −
(1 + F) × 100%
Where: M = Receive margin (%)
N = Ratio of bit rate to clock (N = 372)
D = Clock duty (D = 0 to 1.0)
L = Frame length (L = 10)
F = Absolute value of clock frequency deviation
Using this equation, the receive margin when F = 0 and D = 0.5 is as follows:
M = (0.5 – 1/2 × 372) × 100% = 49.866%