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Rev. 5.00, 09/03, page 97 of 760
• CPU address error
Conditions:
a. Instruction fetch from odd address (4n + 1, 4n + 3)
b. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
c. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
4n + 3)
d. Virtual space accessed in user mode in the area H'80000000 to H'FFFFFFFF
Operations: The virtual address (32 bits) that caused the exception is set in TEA. PC and
SR of the instruction that generated the exception are saved to SPC and SSR, respectively.
If the exception occurred during a read, H'0E0 is set in EXPEVT; if the exception occurred
during a write, H'100 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a
branch occurs to PC = VBR + H'0100. See section 3.5.5, Processing Flow in Event of
MMU Exception, for more information.
• Unconditional trap
Conditions: TRAPA instruction executed
Operations: The exception is a processing-completion type, so PC of the instruction after
the TRAPA instruction is saved to SPC. SR from the time when the TRAPA instruction
was executing is saved to SSR. The 8-bit immediate value in the TRAPA instruction is
quadrupled and set in TRA (9–0). H'160 is set in EXPEVT. The BL, MD, and RB bits in
SR are set to 1 and a branch occurs to PC = VBR + H'0100.
• Illegal general instruction exception
Conditions:
a. When undefined code not in a delay slot is decoded
Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S,
BF/S
Undefined instruction: H'Fxxx
b. When a privileged instruction not in a delay slot is decoded in user mode
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; Instructions that access
GBR with LDC/STC are not privileged instructions and therefore do not apply.
Operations: PC and SR of the instruction that generated this instruction are saved to SPC
and SSR, respectively. H'180 is set in EXPEVT. The BL, MD, and RB bits in SR are set to
1 and a branch occurs to PC = VBR + H'100. When an undefined code other than H'Fxxx is
decoded, operation cannot be guaranteed.