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Rev. 5.00, 09/03, page 390 of 760
12.1.2 Block Diagram
Figure 12.1 shows a block diagram of the TMU.
TOCR
Prescaler
TSTR
TCR0
TCNT0
Module bus
Internal bus
TCOR0
TCR1
TCNT1
TCOR1
Counter
controller
TCLK
Pφ
RTCCLK
TUNI0
Bus interface
Ch. 0
Interrupt
controller
Interrupt
controller
Interrupt
controller
Counter
controller
Counter
controller
TUNI1
TUNI2
TICPI2
TCR2
TCPR2
TCNT2
TCOR2
TMU
Ch. 1
Ch. 2
Clock
controller
TOCR:
TSTR:
TCR:
Legend
Timer output control register
Timer start register
TCNT:
TCOR:
TCPR2:
32-bit timer counter
32-bit timer constant register
32-bit input capture registerTimer control register
Figure 12.1 Block Diagram of TMU