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Rev. 5.00, 09/03, page 244 of 760
Bits 4 and 3—Area 2 Wait Control (A2W1, A2W0): Specify the number of wait states inserted
in physical space area 2.
• For Ordinary Memory
Description
Bit 4: A2W0 Bit 3: A2W0 Inserted Wait States W
WW
WA
AA
AI
II
IT
TT
T Pin
0 0 0 Ignored
1 1 Enabled
1 0 2 Enabled
1 3 Enabled (Initial value)
• For Synchronous DRAM
Description
Bit 4: A2W1 Bit 3: A2W0 Synchronous DRAM: CAS Latency
001
11
102
1 3 (Initial value)
Bits 2 to 0—Area 0 Wait Control (A0W2, A0W1, A0W0): Specify the number of wait states
inserted in physical space area 0. Also specify the burst pitch for burst transfer.
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Bit 2:
A0W2
Bit 1:
A0W1
Bit 0:
A0W0
Inserted
Wait States W
WW
WA
AA
AI
II
IT
TT
T Pin
Number of States
Per Data Transfer W
WW
WA
AA
AI
II
IT
TT
T Pin
0 0 0 0 Ignored 2 Enabled
1 1 Enabled 2 Enabled
1 0 2 Enabled 3 Enabled
1 3 Enabled 4 Enabled
1 0 0 4 Enabled 4 Enabled
1 6 Enabled 6 Enabled
1 0 8 Enabled 8 Enabled
110
(Initial value)
Enabled 10 Enabled