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Rev. 5.00, 09/03, page 664 of 760
23.3.1 Clock Timing
Table 23.5 Clock Timing
VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Item Symbol Min Max Unit Figure
EXTAL clock input frequency (clock mode 0) f
EX
25 66.67 MHz 23.1
EXTAL clock input cycle time (clock mode 0) t
EXcyc
15 40 ns
EXTAL clock input frequency (clock mode 1) f
EX
6.25 16.67 MHz
EXTAL clock input cycle time (clock mode 2) t
EXcyc
60 160 ns
EXTAL clock input low pulse width t
EXL
1.5 — ns
EXTAL clock input high pulse width t
EXH
1.5 — ns
EXTAL clock input rise time t
EXR
—6 ns
EXTAL clock input fall time t
EXF
—6 ns
CKIO clock input frequency f
CKI
20 66 MHz 23.2
CKIO clock input cycle time t
CKIcyc
15.2 40 ns
CKIO clock input low pulse width t
CKIL
1.5 — ns
CKIO clock input high pulse width t
CKIH
1.5 — ns
CKIO clock input rise time t
CKIR
—6 ns
CKIO clock input fall time t
CKIF
—6 ns
CKIO clock output frequency f
OP
25 66 MHz 23.3
CKIO clock output cycle time t
cyc
15.2 40 ns
CKIO clock output low pulse width t
CKOL
3—ns
CKIO clock output high pulse width t
CKOH
3—ns
CKIO clock output rise time t
CKOR
—5 ns
CKIO clock output fall time t
CKOF
—5 ns
CKIO2 clock output delay time t
CK2D
–3 3 ns
CKIO2 clock output rise time t
CK20R
—7 ns
CKIO2 clock output fall time t
CK20F
—7 ns
Power-on oscillation settling time t
OSC1
10 — ms 23.4
RESETP setup time t
RESPS
20 — ns 23.4, 23.5
RESETM setup time t
RESMS
6—ns
RESETP assert time t
RESPW
20 — t
cyc
RESETM assert time t
RESMW
20 — t
cyc
Standby return oscillation settling time 1 t
OSC2
10 — ms 23.5
Standby return oscillation settling time 2 t
OSC3
10 — ms 23.6
Standby return oscillation settling time 3 t
OSC4
11 — ms 23.7
PLL synchronization settling time 1
(standby canceled)
t
PLL1
100 — µs 23.8, 23.9
PLL synchronization settling time 2
(multiplication rete modified)
t
PLL2
100 — µs 23.10
IRQ/IRL interrupt determination time
(RTC used and standby mode)
t
IRLSTB
100 — µs 23.9