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Rev. 5.00, 09/03, page 669 of 760
EXTAL input
*1
(CKIO input)
CKIO output
*2
(PLL output)
Internal clock
Multiplication rate modified
t
PLL2
Notes: 1. CKIO input in clock mode 7
2. PLL output in other than clock mode 7
Figure 23.10 PLL Synchronization Settling Time when Frequency Multiplication
Rate Modified