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Rev. 5.00, 09/03, page 324 of 760
Table 10.15 MCSCRx Settings and M
MM
MC
CC
CS
SS
S[
[[
[x
xx
x]
]]
] Assertion Conditions (x: 0–7)
MCSCRx Settings M
MM
MC
CC
CS
SS
S[
[[
[x
xx
x]
]]
] Assertion Conditions
CS2/0 CAP1 CAP0 A25 A24 A23 A22 C
CC
CS
SS
S0
00
0C
CC
CS
SS
S2
22
2 Address Bus A [25:0] Notes
0110———LHH'0000000 to H'1FFFFFF 256-Mbit ROM
1 — — — L H H'2000000 to H'3FFFFFF
1 0 0 0 — — L H H'0000000 to H'0FFFFFF 128-Mbit ROM
0 1 — — L H H'1000000 to H'1FFFFFF
1 0 — — L H H'2000000 to H'2FFFFFF
1 1 — — L H H'3000000 to H'3FFFFFF
0 1 0 0 0 — L H H'0000000 to H'07FFFFF 64-Mbit ROM
0 0 1 — L H H'0800000 to H'0FFFFFF
0 1 0 — L H H'1000000 to H'17FFFFF
0 1 1 — L H H'1800000 to H'1FFFFFF
1 0 0 — L H H'2000000 to H'27FFFFF
1 0 1 — L H H'2800000 to H'2FFFFFF
1 1 0 — L H H'3000000 to H'37FFFFF
1 1 1 — L H H'3800000 to H'3FFFFFF
0 0 0 0 0 0 L H H'0000000 to H'03FFFFF 32-Mbit ROM
0 0 0 1 L H H'0400000 to H'07FFFFF
0 0 1 0 L H H'0800000 to H'0BFFFFF
0 0 1 1 L H H'0C00000 to H'0FFFFFF
0 1 0 0 L H H'1000000 to H'13FFFFF
0 1 0 1 L H H'1400000 to H'17FFFFF
0 1 1 0 L H H'1800000 to H'1BFFFFF
0 1 1 1 L H H'1C00000 to H'1FFFFFF
1 0 0 0 L H H'2000000 to H'23FFFFF
1 0 0 1 L H H'2400000 to H'27FFFFF
1 0 1 0 L H H'2800000 to H'2BFFFFF
1 0 1 1 L H H'2C00000 to H'2FFFFFF
1 1 0 0 L H H'3000000 to H'33FFFFF
1 1 0 1 L H H'3400000 to H'37FFFFF
1 1 1 0 L H H'3800000 to H'3BFFFFF
1 1 1 1 L H H'3C00000 to H'3FFFFFF