Filter
Top Products
Rev. 5.00, 09/03, page 281 of 760
Table 10.14 Example of Correspondence between SH7709S and Synchronous DRAM
Address Pins (AMX [3:0] = 0100 (32-Bit Bus Width))
SH7709S Address Pin Synchronous DRAM Address Pin
RAS Cycle CAS Cycle Function
A15 A23 A23 A13(BA1)
A14 A22 A22 A12(BA0)
BANK select bank address
A13 A21 A13 A11 Address
A12 A20 L/H A10 Address precharge setting
A11 A19 A11 A9
A10 A18 A10 A8
A9 A17 A9 A7
A8 A16 A8 A6
A7 A15 A7 A5
A6 A14 A6 A4
A5 A13 A5 A3
A4 A12 A4 A2
A3 A11 A3 A1
A2 A10 A2 A0
Address
A1 A9 A1 Not used
A0 A0 A0 Not used
Burst Read: In the example in figure 10.15 it is assumed that four 2M × 8-bit synchronous
DRAMs are connected and a 32-bit data width is used, and the burst length is 1. Following the Tr
cycle in which ACTV command output is performed, a READ command is issued in the Tc1, Tc2,
and Tc3 cycles, and a READA command in the Tc4 cycle, and the read data is accepted at the
rising edge of the external command clock (CKIO) from cycle Td1 to cycle Td4. The Tpc cycle is
used to wait for completion of auto-precharge based on the READA command inside the
synchronous DRAM; no new access command can be issued to the same bank during this cycle,
but access to synchronous DRAM for another area is possible. In the SH7709S, the number of Tpc
cycles is determined by the TPC bit specification in MCR, and commands cannot be issued for the
same synchronous DRAM during this interval.
The example in figure 10.14 shows the basic cycle. To connect low-speed synchronous DRAM,
the cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV
command output cycle, Tr, to the READ command output cycle, Tc1, can be specified by the
RCD bits in MCR, with values of 0 to 3 specifying 1 to 4 cycles, respectively. In case of 2 or more
cycles, a Trw cycle, in which an NOP command is issued for the synchronous DRAM, is inserted
between the Tr cycle and the Tc cycle. The number of cycles from READ and READA command
output cycles Tc1-Tc4 to the first read data latch cycle, Td1, can be specified as 1 to 3 cycles