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Rev. 5.00, 09/03, page xix of xliv
5.1.2 Cache Structure .................................................................................................... 103
5.1.3 Register Configuration ......................................................................................... 105
5.2 Register Description.......................................................................................................... 105
5.2.1 Cache Control Register (CCR)............................................................................. 105
5.2.2 Cache Control Register 2 (CCR2)........................................................................ 106
5.3 Cache Operation................................................................................................................ 109
5.3.1 Searching the Cache............................................................................................. 109
5.3.2 Read Access ......................................................................................................... 111
5.3.3 Prefetch Operation................................................................................................ 111
5.3.4 Write Access ........................................................................................................ 111
5.3.5 Write-Back Buffer................................................................................................ 111
5.3.6 Coherency of Cache and External Memory.......................................................... 112
5.4 Memory-Mapped Cache.................................................................................................... 112
5.4.1 Address Array ...................................................................................................... 112
5.4.2 Data Array............................................................................................................ 113
5.4.3 Examples of Usage............................................................................................... 115
Section 6 Interrupt Controller (INTC)
........................................................................... 117
6.1 Overview........................................................................................................................... 117
6.1.1 Features ................................................................................................................ 117
6.1.2 Block Diagram ..................................................................................................... 118
6.1.3 Pin Configuration ................................................................................................. 119
6.1.4 Register Configuration ......................................................................................... 120
6.2 Interrupt Sources ............................................................................................................... 121
6.2.1 NMI Interrupt....................................................................................................... 121
6.2.2 IRQ Interrupts ...................................................................................................... 121
6.2.3 IRL Interrupts....................................................................................................... 122
6.2.4 PINT Interrupts .................................................................................................... 124
6.2.5 On-Chip Peripheral Module Interrupts................................................................. 124
6.2.6 Interrupt Exception Handling and Priority ........................................................... 125
6.3 INTC Registers.................................................................................................................. 131
6.3.1 Interrupt Priority Registers A to E (IPRA–IPRE) ................................................ 131
6.3.2 Interrupt Control Register 0 (ICR0) ..................................................................... 132
6.3.3 Interrupt Control Register 1 (ICR1) ..................................................................... 133
6.3.4 Interrupt Control Register 2 (ICR2) ..................................................................... 136
6.3.5 PINT Interrupt Enable Register (PINTER) .......................................................... 137
6.3.6 Interrupt Request Register 0 (IRR0)..................................................................... 138
6.3.7 Interrupt Request Register 1 (IRR1)..................................................................... 140
6.3.8 Interrupt Request Register 2 (IRR2)..................................................................... 141
6.4 INTC Operation................................................................................................................. 143
6.4.1 Interrupt Sequence................................................................................................ 143
6.4.2 Multiple Interrupts................................................................................................ 145
6.5 Interrupt Response Time ................................................................................................... 145