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Rev. 5.00, 09/03, page 13 of 760
Number of Pins
FP-208C
FP-208E BP-240A Pin Name I/O Description
106 U18 RAS3L/PTJ[0] O / I/O Lower 32 M / 64 Mbytes address
(SDRAM) RAS / input/output port J
107 U19 PTJ[1] O / I/O Input/output port J
*
5
108 R18 CASL/PTJ[2] O / I/O Lower 32 M / 64 Mbytes address
(SDRAM) CAS / input/output port J
109 T19 VssQ — Input/output power supply (0 V)
110 T17 CASU/PTJ[3] O / I/O Lower 32 Mbytes address
(SDRAM) CAS / input/output port J
111 R19 VccQ — Input/output power supply (3.3 V)
112 U17 PTJ[4] I/O Input/output port J
113 R17 PTJ[5] I/O Input/output port J
114 R16 DACK0/PTD[5] O / I/O DMA acknowledge 0 / input/output
port D
115 P19 DACK1/PTD[7] O / I/O DMA acknowledge 1 / input/output
port D
116 P18 PTE[6] I/O Input/output port E
117 P17 PTE[3] I/O Input/output port E
118 P16 RAS3U/PTE[2] O / I/O Upper 32 Mbytes address
(SDRAM) RAS / input/output port
E
119 N19 PTE[1] I/O Input/output port E
120 N18 TDO/PTE[0] O / I/O Test data output / input/output
port E
121 N17 BACK O Bus acknowledge
122 N16 BREQ I Bus request
123 M19 WAIT I Hardware wait request
124 M18 RESETM I Manual reset request
125 M17 ADTRG/PTH[5] I Analog trigger / input port H
126 M16 IOIS16/PTG[7] I IOIS16 (PCMCIA) / input port G
127 L19 ASEMD0/PTG[6] I ASE mode
*
4
/ input port G
128 L18 ASEBRKAK/PTG[5] O/I ASE break acknowledge / input
port G
129 L16 PTG[4]/CK102 I Input port G / clock output