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Rev. 5.00, 09/03, page 334 of 760
11.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)
DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit readable/writable registers that
specify the destination address of a DMA transfer. These registers include a count function, and
during a DMA transfer, these registers indicate the next destination address.
To transfer data in 16-bit or 32-bit units, make sure to specify a destination address with a 16-byte
boundary (16n address).
An undefined value will be returned in a reset. The previous value is retained in standby mode.
Bit: 31 30 29 28 27 26 25 24
Initial value:————————
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23 22 21 20 … 0
…
Initial value: — — — — … —
R/W: R/W R/W R/W R/W … R/W