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Rev. 5.00, 09/03, page 442 of 760
Bit 4—Framing Error (FER): Indicates that data reception aborted due to a framing error in
asynchronous mode.
Bit 4: FER Description
0 Receiving is in progress or has ended normally
*
1
(Initial value)
[Clearing conditions]
(1) FER is cleared to 0 when the chip is reset or enters standby mode.
(2) When software reads FER after it has been set to 1, then writes 0 to FER.
1 A receive framing error occurred
[Setting condition]
FER is set to 1 if the stop bit at the end of receive data is checked and found to
be 0.
*
2
Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which
retains its previous value.
2. When the stop bit length is two bits, only the first bit is checked. The second stop bit is
not checked. When a framing error occurs, the SCI transfers the receive data into
SCRDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1.
In synchronous mode, serial transmitting is also disabled.
Bit 3—Parity Error (PER): Indicates that data reception (with parity) aborted due to a parity
error in asynchronous mode.
Bit 3: PER Description
0 Receiving is in progress or has ended normally
*
1
(Initial value)
[Clearing conditions]
(1) PER is cleared to 0 when the chip is reset or enters standby mode.
(2) When software reads PER after it has been set to 1, then writes 0 to PER.
1 A receive parity error occurred
*
2
[Setting condition]
PER is set to 1 if the number of 1s in receive data, including the parity bit, does
not match the even or odd parity setting of the parity mode bit (O/E) in the serial
mode register (SCSMR).
Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the PER bit, which
retains its previous value.
2. When a parity error occurs, the SCI transfers the receive data into SCRDR but does not
set RDRF. Serial receiving cannot continue while PER is set to 1. In synchronous
mode, serial transmitting is also disabled.