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Rev. 5.00, 09/03, page 236 of 760
Bit 15—Pin A25 to A0 Pull-Up (PULA): Specifies whether or not pins A25 to A0 are pulled up
for 4 cycles immediately after BACK is asserted.
Bit 15: PULA Description
0 Not pulled up (Initial value)
1 Pulled up
Bit 14—Pin D31 to D0 Pull-Up (PULD): Specifies whether or not pins D31 to D0 are pulled up
when not in use.
Bit 14: PULD Description
0 Not pulled up (Initial value)
1 Pulled up
Bit 13—Hi-Z Memory Control (HIZMEM): Specifies the state of A25–A0, BS, CS, RD/WR,
WE/DQM, RD, CE2A, CE2B and DRAK0/1 in standby mode.
Bit 13: HIZMEM Description
0 A25–A0, BS, CS, RD/WR, WE/DQM, RD, CE2A, CE2B and DRAK0/1 are
Hi-Z in standby mode (Initial value)
1 A25–A0, BS, CS, RD/WR, WE/DQM, RD, CE2A, CE2B and DRAK0/1 are
high in standby mode
Bit 12—High-Z Control (HIZCNT): Specifies the state of the RAS and CAS signals in standby
mode and when the bus is released.
Bit 12: HIZCNT Description
0 RAS and CAS signals are high-impedance (High-Z) in standby mode and
when bus is released (Initial value)
1 RAS and CAS signals are driven in standby mode and when bus is released
Bit 11—Endian Flag (ENDIAN): Samples the value of the external pin designating the endian in
a power-on reset. The endian for all physical spaces is decided by this bit, which is read-only.
Bit 11: ENDIAN Description
0 (On reset) Endian setting external pin (MD5) is low. Indicates the SH7709S
is set as big-endian
1 (On reset) Endian setting external pin (MD5) is high. Indicates the SH7709S
is set as little-endian