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Rev. 5.00, 09/03, page 700 of 760
CKIO
T
pcm0
T
pcm0w
T
pcm1
T
pcm1w
T
pcm1w
T
pcm2
T
pcm2w
A25 to A0
CExx
RD/WR
RD
(read)
D15 to D0
(read)
WE1
(write)
D15 to D0
(write)
BS
DACKn
WAIT
t
AD
t
CSD1
t
RWD
t
AD
t
CSD1
t
RWD
t
WDH4
t
RSD
t
RSD
t
DAKD1
t
DAKD1
t
WED
t
WDD1
t
WED
t
WDH1
t
RDH1
t
BSD
t
WTS
t
WTH
t
WTS
t
WTH
t
RDS1
t
BSD
Figure 23.41 PCMCIA Memory Bus Cycle
(TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1)