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Rev. 5.00, 09/03, page 140 of 760
6.3.7 Interrupt Request Register 1 (IRR1)
IRR1 is an 8-bit read-only register that indicates whether DMAC or IrDA interrupt requests have
been generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.
Bit:76543210
TXI1R BRI1R RXI1R ERI1R DEI3R DEI2R DEI1R DEI0R
Initial value:00000000
R/W:RRRRRRRR
Bit 7—TXI1 Interrupt Request (TXI1R): Indicates whether a TXI1 (IrDA) interrupt request has
been generated.
Bit 7: TXI1 Description
0 TXI1 interrupt request not generated (Initial value)
1 TXI1 interrupt request generated
Bit 6—BRI1 Interrupt Request (BRI1R): Indicates whether a BRI1 (IrDA) interrupt request has
been generated.
Bit 6: BRI1R Description
0 BRI1 interrupt request not generated (Initial value)
1 BRI1 interrupt request generated
Bit 5—RXI1 Interrupt Request (RXI1R): Indicates whether an RXI1 (IrDA) interrupt request
has been generated.
Bit 5: RXI1R Description
0 RXI1 interrupt request not generated (Initial value)
1 RXI1 interrupt request generated
Bit 4—ERI1 Interrupt Request (ERI1R): Indicates whether an ERI1 (IrDA) interrupt request
has been generated.
Bit 4: ERI1R Description
0 ERI1 interrupt request not generated (Initial value)
1 ERI1 interrupt request generated