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Rev. 5.00, 09/03, page 256 of 760
10.2.10 Refresh Time Constant Register (RTCOR)
The refresh time constant register (RTCOR) specifies the upper-limit value of RTCNT. The values
of RTCOR and RTCNT (lower 8 bits) are constantly compared. When the values match, the
compare match flag (CMF) in RTCSR is set and RTCNT is cleared to 0. When the refresh bit
(RFSH) in the individual memory control register (MCR) is set to 1 and the refresh mode is set to
auto refresh, a memory refresh cycle occurs when the CMF bit is set. RTCOR is a
readable/writable register. RTCOR is initialized to H'00 by a power-on reset. It is not initialized by
a manual reset or in standby mode, but holds its contents. Make the RTCOR setting before setting
bits CKS2 to CKS0 in RTCSR.
Note: The method of writing to RTCOR differs from that for general registers to ensure that
RTCOR is not rewritten incorrectly. Use a word transfer instruction to set the upper byte
as B'10100101 and the lower byte as the write data. For details, see section 10.2.12,
Cautions on Accessing Refresh Control Related Registers.
Bit: 15 14 13 12 11 10 9 8
Initial value:00000000
R/W:————————
Bit:76543210
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
10.2.11 Refresh Count Register (RFCR)
The refresh count register (RFCR) counts the number of refreshing. When RFCR exceeds the
count limit value set in the LMTS bit in RTCSR, the OVF bit in RTCSR is set and RFCR is
cleared. RFCR is a 10-bit readable/writable counter. RFCR is initialized to H'0000 by a power-on
reset. RFCR continues incrementing in a manual reset. It is not initialized by in standby mode, but
holds its contents.
Note: The method of writing to RFCR differs from that for general registers to ensure that RFCR
is not rewritten incorrectly. Use a word transfer instruction to set the six bits starting from
the MSB in the upper byte as B'101001, and the remaining bits as the write data. For
details, see section 10.2.12, Cautions on Accessing Refresh Control Related Registers.