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Rev. 5.00, 09/03, page 587 of 760
Section 19 I/O Ports
19.1 Overview
The SH7709S has twelve 8-bit ports (ports A to L and SC). All port pins are multiplexed with
other pin functions (the pin function controller (PFC) handles the selection of pin functions and
pull-up MOS control). Each port has a data register which stores data for the pins.
19.2 Port A
Port A is an 8-bit input/output port with the pin configuration shown in figure 19.1. Each pin has
an input pull-up MOS, which is controlled by the port A control register (PACR) in the PFC.
PTA7 (input/output) / D23 (input/output
)
PTA6 (input/output) / D22 (input/output
)
PTA5 (input/output) / D21 (input/output
)
PTA4 (input/output) / D20 (input/output
)
PTA3 (input/output) / D19 (input/output
)
PTA2 (input/output) / D18 (input/output
)
PTA1 (input/output) / D17 (input/output
)
PTA0 (input/output) / D16 (input/output
)
Port A
Figure 19.1 Port A
19.2.1 Register Description
Table 19.1 summarizes the port A register.
Table 19.1 Port A Register
Name Abbreviation R/W Initial Value Address Access Size
Port A data register PADR R/W H'00 H'04000120
(H'A4000120)
*
8
Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either
access this register from the P2 area of logical space or else make an appropriate setting
using the MMU so that this register is not cached.
* When address translation by the MMU does not apply, the address in parentheses
should be used.