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Rev. 5.00, 09/03, page 537 of 760
16.3 Operation
16.3.1 Overview
For serial communication, the SCIF has an asynchronous mode in which characters are
synchronized individually. Refer to section 14.3.2, Operation in Asynchronous Mode. The SCIF
has a 16-byte FIFO buffer for both transmit and receive operations, reducing the overhead of the
CPU, and enabling continuous high-speed communication. Moreover, it has RTS and CTS signals
as modem control signals. The transmission format is selected in the serial mode register
(SCSMR), as shown in table 16.7. The SCIF clock source is selected by the combination of the
CKE1 and CKE0 bits in the serial control register (SCSCR), as shown in table 16.8.
• Data length is selectable: 7 or 8 bits.
• Parity and multiprocessor bits are selectable, as is the stop bit length (1 or 2 bits). The
combination of the preceding selections constitutes the communication format and character
length.
• In receiving, it is possible to detect framing errors (FER), parity errors (PER), receive FIFO
data full, receive data ready, and breaks.
• In transmitting, it is possible to detect transmit FIFO data empty.
• The number of stored data bytes is indicated for both the transmit and receive FIFO registers.
• An internal or external clock can be selected as the SCIF clock source.
When an internal clock is selected, the SCIF operates using the on-chip baud rate
generator, and can output a serial clock signal with a frequency 16 times the bit rate.
When an external clock is selected, the external clock input must have a frequency 16 times
the bit rate. (The on-chip baud rate generator is not used.)
Table 16.7 SCSMR Settings and SCIF Communication Formats
SCSMR Settings SCIF Communication Format
Mode
Bit 6
CHR
Bit 5
PE
Bit 3
STOP
Data
Length
Parity
Bit Stop Bit Length
Asynchronous 0 0 0 8-bit Not set 1 bit
12 bits
10 Set 1 bit
12 bits
100 7-bitNot set1 bit
12 bits
10 Set 1 bit
12 bits