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Rev. 5.00, 09/03, page 387 of 760
11.6 Usage Notes
1. The DMA channel control registers (CHCR0–CHCR3) can be accessed with any data size. The
DMA operation register (DMAOR) must be accessed by byte (8 bits) or word (16 bits); other
registers must be accessed by word (16 bits) or longword (32 bits).
2. Before rewriting the RS0–RS3 bits in CHCR0–CHCR3, first clear the DE bit to 0 (when
rewriting CHCR with a byte address, be sure to set the DE bit to 0 in advance).
3. Even if an NMI interrupt is input when the DMAC is not operating, the NMIF bit in DMAOR
will be set.
4. Before entering standby mode, the DME bit in DMAOR must be cleared to 0 and the transfers
accepted by the DMAC completed.
5. The on-chip peripherals which the DMAC can access are the IrDA, SCIF, A/D converter, D/A
converter, and I/O ports. Do not access other peripherals with the DMAC.
6. When starting up the DMAC, set CHCR or DMAOR last. Normal operation is not guaranteed
if settings for another register are made last.
7. Even if the maximum number of transfers are performed in the same channel after the
DMATCR count reaches 0 and DMA transfer ends normally, write 0 to DMATCR.
Otherwise, normal DMA transfer may not be performed.
8. When using the address reload function, specify burst mode as the transfer mode. In cycle-steal
mode, normal DMA transfer may not be performed.
9. When using the address reload function, set a multiple of four in DMATCR. Normal operation
is not guaranteed if other values are specified.
10. When detecting an external request at the falling edge, keep the external request pin high when
setting the DMAC.
11. Do not access the space from H'4000062 to H'400006F, which is not used in the DMAC.
Accessing this space may cause malfunctions.
12. The WAIT signal is ignored in the case of a write to external address space in dual address
mode with 16-byte transfer, or transfer from an external device with DACK to external address
space in signal address mode with 16-byte transfer.
13. DMAC transfers should not be performed in the sleep mode under conditions other than when
the clock ratio of Iφ (on-chip clock) to Bφ (bus clock) is 1:1.
14. When the following three conditions are all met, the frequency control register (FRQCR)
should not be changed while a DMAC transfer is in progress.
• Bits IFC2 to IFC0 are changed.
• STC2 to STC0 in FRQCR are not changed.
• The clock ratio of Iφ (on-chip clock) to Bφ (bus clock) after the change is other than 1:1.