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Rev. 5.00, 09/03, page 380 of 760
Compare Match Constant Register 0 (CMCOR0)
Compare match constant register 0 (CMCOR0) is a 16-bit register that sets the CMCNT0 compare
match period.
CMCOR0 is initialized to H'FFFF by a reset, but retains its previous value in standby mode.
Bit: 15 14 13 12 11 10 9 8
Initial value:11111111
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit:76543210
Initial value:11111111
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
11.4.3 Operation
Period Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in the CMCSR0 register and the
STR bit in CMSTR is set to 1, CMCNT0 begins incrementing on the selected clock. When the
CMCNT counter value matches that of CMCOR0, the CMCNT0 counter is cleared to H'0000 and
the CMF flag in the CMCSR0 register is set to 1. The CMCNT0 counter begins counting up again
from H'0000.
Figure 11.25 shows the compare match counter operation.
Counter cleared by
CMCOR0 compare match
CMCNT0 value
CMCOR0
H'0000
Time
Figure 11.25 Counter Operation