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Rev. 5.00, 09/03, page 618 of 760
20.2.2 A/D Control/Status Register (ADCSR)
Bit:76543210
ADF ADIE ADST MULTI CKS CH2 CH1 CH0
Initial value:00000000
R/W: R/(W)
*
R/W R/W R/W R/W R/W R/W R/W
Note: * Write 0 to clear the flag.
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'00 by a reset and in standby mode.
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7: ADF Description
0 [Clearing conditions] (Initial value)
(1) Cleared by reading ADF while ADF = 1, then writing 0 to ADF
(2) Cleared when DMAC is activated by ADI interrupt and ADDR is read
1 [Setting conditions]
(1) Single mode: A/D conversion ends
(2) Multi mode: A/D conversion ends on all selected channels
(3) Scan mode: A/D conversion ends on all selected channels
Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the
end of A/D conversion. The ADIE bit should be set while the A/D conversion stops.
Bit 6: ADIE Description
0 A/D end interrupt request (ADI) is disabled (Initial value)
1 A/D end interrupt request (ADI) is enabled