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Rev. 5.00, 09/03, page 344 of 760
Bit 2—Address Error Flag Bit (AE): Indicates that an address error occurred by the DMAC. If
this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write
1 to this bit. This bit can only be cleared by writing 0 after reading 1.
Bit 2: AE Description
0 No DMAC address error; DMA transfer is enabled (Initial value)
Clearing conditions: Writing 0 to AE after reading AE = 1
Power-on reset, manual reset
1 DMAC address error; DMA transfer is disabled
This bit is set by occurrence of a DMAC address error
Bit 1—NMI Flag Bit (NMIF): Indicates that an NMI is input. This bit is set regardless of
whether the DMAC is in the operating or halted state. The CPU cannot write 1 to this bit. Only 0
can be written to clear this bit after 1 is read.
Bit 1: NMIF Description
0 No NMI input; DMA transfer is enabled (Initial value)
Clearing conditions: Writing 0 to NMIF after reading NMIF = 1
Power-on reset, manual reset
1 NMI input; DMA transfer is disabled
This bit is set by occurrence of an NMI interrupt
Bit 0—DMA Master Enable Bit (DME): Enables or disables the DMAC on all channels. If the
DME bit and the DE bit corresponding to each channel in CHCR are set to 1, transfer is enabled
on the corresponding channel. If this bit is cleared during transfer, transfer on all the channels will
be terminated.
Even if the DME bit is set, transfer is not enabled if the TE bit is 1 or the DE bit is 0 in CHCR, or
the NMIF or AE bit is 1 in DMAOR.
Bit 0: DME Description
0 DMA transfer disabled on all channels (Initial value)
1 DMA transfer enabled on all channels